An active row is thus cached in the row buffer. Reading a row into the row buffer is called activating the row. This is because for reading automatically discharges the capacitor and since writes rarely rewrite the entire row. When you read or write from/to DRAM an entire row is first read into a so called so called row buffer. Thus a row stores 8kb or 64kb of data depending on the exact kind of DRAM you have in front of you. Each cell stores one bit and consists of a transistor for control and a capacitor which stores charge to signify bit is equal to 1 and no charge when bit is equal to 0 (on some chips the encoding is reversed). There are 32k rows in the matrix and 16k or 512k cells per row. Inside a bank you’d find a two dimensional matrix of memory cells. The banks are in the physical individual chips you can see. Each rank again consists of a number of banks. If you look at the DIMM most DIMMs will have chips on both sides. If you buy a modern memory module for your PC, you’re buying a DIMM. With so much going on I found it worthwhile updating this blog post to be in line with the latest developments and to fix up a few minor details.Ĭurrent DRAM comes in modules called DIMM’s. As I had predicted the summer was going to be interesting in terms of row hammer and it certainly appears I was right about that. This is the first updated version of my original “Row hammer the short summary” blog post.
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